Patent · US Active

SRAM memory with reference bias cell

US7787286B2 · kind B2 · utility

4Cited by

7References

13Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventor

Olivier Thomas · Saint-Martin-d'Hères, FR

Key dates

Filing date	Sep 23, 2008
Grant date	Aug 31, 2010
Priority date	—
Expiry date	Jan 23, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/14
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A random access memory microelectronic device, comprising a plurality of cells comprising respectively: a plurality of transistors forming a bistable, a first storage node and a second storage node, a first double gate access transistor to the first storage node and a second double gate access transistor to the second storage node, a first gate of the first access transistor and a first gate of the second access transistor being linked to a first word line, a second gate of the first access transistor and a second gate of the second access transistor being linked to a second word line, the device being moreover equipped: with a reference memory cell provided to deliver a bias potential intended to be applied to one of the respective word lines of one or several given cells of said plurality of cells during reading access of said given cells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.