Asymmetrical bus for bus link width optimization of a graphics system
US7788439B1 · kind B1 · utility
11Cited by
13References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 16, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Feb 27, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.