System and method for repairing a memory
US7788551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Aug 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.