Method of manufacturing at least one semiconductor component and memory cells

US7790516B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Josef Willer · Riemerling, DE
• Nicolas Nagel · Yokohama, JP

Key dates

• Filing date: Jul 10, 2006
• Grant date: Sep 7, 2010
• Expiry date: Feb 17, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/69

Abstract

A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and annealed. The patterned layer structure is at least partially removed. Replacing material is formed in the region in which the patterned layer structure has been removed, thereby forming the at least one NAND-coupled semiconductor component.