Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures

US7790524B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Wagdi W. Abadeer · Jericho, US
• Kiran V. Chatty · Williston, US
• Robert J. Gauthier, Jr. · South Burlington, US
• Jed H. Rankin · South Burlington, US
• Yun Shi · South Burlington, US
• William R. Tonti · South Burlington, US

Key dates

• Filing date: Jan 11, 2008
• Grant date: Sep 7, 2010
• Expiry date: Feb 20, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0411

Abstract

Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a floating gate electrode, a semiconductor body, and a control gate electrode separated from the semiconductor body by the floating gate electrode. The floating gate electrode, the control gate electrode, and the semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are respectively separated by dielectric layers. The dielectric layers may each be composed of thermal oxide layers grown on confronting sidewalls of the semiconductor body, the floating gate electrode, and the control gate electrode. An optional deposited dielectric material may fill any remaining gap between either pair of the thermal oxide layers.