Method to reduce junction leakage through partial regrowth with ultrafast anneal and structures formed thereby
US7790587B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Nov 7, 2006 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Aug 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and associated structures of forming a microelectronic device are described. Those methods may include creating an amorphous region in source/drain regions of a substrate by ion implantation with an electrically neutral dopant, annealing with a first anneal that removes defects without completely re-crystallizing the amophous region, ion implantation of electrically active dopant to a depth shallower than the remaining amorphous region, followed by a second anneal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.