Double-gate semiconductor devices having gates with different work functions and methods of manufacture thereof
US7791140B2 · kind B2 · utility
3Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2007 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Jun 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the second gate facing the fin being formed of a metal silicide compound. The different compositions of the two gates provide different respective work functions to reduce short channel effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.