Multi-state resistive memory element, multi-bit resistive memory cell, operating method thereof, and data processing system using the memory element
US7791923B2 · kind B2 · utility
6Cited by
2References
17Claims
0Family size
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Key dates
| Filing date | Jan 3, 2007 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Jan 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.