Semiconductor device and semiconductor signal processing apparatus
US7791962B2 · kind B2 · utility
408Cited by
4References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 16, 2008 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Jun 20, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.