Processing pipeline having parallel dispatch and method thereof
US7793080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2007 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Nov 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor cores each can implement dispatch resources configured to dispatch multiple instructions in parallel to multiple corresponding execution units via separate dispatch buses. The dispatch resources further can opportunistically decode and dispatch instruction operations from multiple threads in parallel so as to increase the dispatch bandwidth. Moreover, some or all of the stages of the processing pipelines of one or more of the processor cores can be configured to implement independent thread selection for the corresponding stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.