Lowering power consumption during logic built-in self-testing (LBIST) via channel suppression
US7793184B2 · kind B2 · utility
5Cited by
7References
9Claims
0Family size
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Key dates
| Filing date | Jan 11, 2007 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Apr 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method, system and computer readable medium for on-chip testing is presented. In one embodiment, the method, system or computer readable medium includes identifying which LBIST channels of a plurality of LBIST channels do not contribute to a particular test and excluding from that particular test each LBIST channel that does not contribute to that particular test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.