Power network analyzer for an integrated circuit design
US7793241B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Nov 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector “I” and conductance matrix “G” are used to solve for voltage drop ΔV, in a matrix equation GΔV=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.