Patent · US Active

Method and system for designing a timing closure of an integrated circuit

US7793254B2 · kind B2 · utility

1Cited by

2References

13Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Patrick John Eichenseer · Austin, US
Ricky Lewelling · Kyle, US
Ziad Sadi · Austin, US

Key dates

Filing date	Jul 18, 2007
Grant date	Sep 7, 2010
Priority date	—
Expiry date	Oct 22, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/3312
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspects further include instantiating one or more smallest repeaters between at least one pair of connected blocks depending upon a drive of a corresponding interconnect, the instantiation of the smallest repeater being based on pre-determined criteria.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.