Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement

US7795105B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Klaus Goller · Dresden, DE
• Olaf Heitzsch · Coswig, DE
• Marion Nichterwitz · Dresden, DE

Key dates

• Filing date: Sep 25, 2006
• Grant date: Sep 14, 2010
• Expiry date: Feb 1, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also relates to a method for producing aligning marks. During the method, a planarization is carried out before material is removed from an auxiliary indentation.