Method of fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel

US7795112B2 · kind B2 · utility

Assignees

• IMEC · BE
• NXP B.V. · NL

Inventors

• Youri Victorovitch Ponomarev · Leuven, BE
• Josine Loo · Leuven, BE

Key dates

• Filing date: Mar 28, 2005
• Grant date: Sep 14, 2010
• Expiry date: Jan 2, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0223
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.