Josine Loo
7Patents
2h-index
6Co-inventors
36Inventor score
Filing activity: Jan 20, 2003 → Mar 6, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8452369B2 | CMOS compatible microneedle structures | Human Necessities | 15 | Active |
| US7838367B2 | Method for the manufacture of a semiconductor device and a semiconductor device obtained through it | Electricity | 3 | Active |
| US7829411B2 | Method and device to form high quality oxide layers of different thickness in one processing step | Electricity | 1 | Expired |
| US7407844B2 | Planar dual gate semiconductor device | Electricity | 1 | Expired |
| US7488669B2 | Method to make markers for double gate SOI processing | Electricity | 0 | Expired |
| US7795112B2 | Method of fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel | Electricity | 0 | Active |
| US7772646B2 | Method of manufacturing a semiconductor device and such a semiconductor device | Emerging Cross-Sectional Technologies | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.