Metal capping of damascene structures to improve reliability using hyper selective chemical-mechanical deposition
US7795150B2 · kind B2 · utility
1Cited by
11References
9Claims
0Family size
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Key dates
| Filing date | Nov 29, 2004 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Apr 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76849
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for improving the reliability of integrated circuits. In one embodiment, the method includes forming a dielectric layer on a semiconductor wafer. A trench is then formed in the dielectric. Thereafter, a conductive interconnect is formed within the trench, wherein the conductive interconnect comprises copper. The conductive interconnect is then etched using an acidic solution. Lastly, a conductive layer is formed on an exposed surface of the etched conductive interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.