Device structures with a self-aligned damage layer and methods for forming such device structures
US7795679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Sep 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26506
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Device structures with a self-aligned damage layer and methods of forming such device structures. The device structure first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate. A third doped region of opposite conductivity type laterally separates the first doped region from the second doped region. A gate structure is disposed on a top surface of the substrate and has a vertically stacked relationship with the third doped region. A first crystalline damage layer is defined within the semiconductor material of the substrate. The first crystalline damage layer has a first plurality of voids surrounded by the semiconductor material of the substrate. The first doped region is disposed vertically between the first crystalline damage layer and the top surface of the substrate. The first crystalline damage layer does not extend laterally into the third doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.