Enabling on-chip features via efuses
US7795899B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2009 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Apr 8, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for enabling on-chip features via efuses. A system comprises an electronic fuse (Efuse) array (EFA) coupled to each features capability register (FCR) within an instantiated computational block. The EFA comprises a plurality of rows wherein programming an row comprises blowing one or more Efuses of the row. A valid row comprises programmed Efuses corresponding to one or more on-chip enabled features. The EFA is further configured to prevent enabling of disabled on-chip features from occurring subsequent to a predetermined point in time, such as the time of shipping the chip to the field for use by end-users, by establishing a particular default state for electronic fuses and rendering unusable any unprogrammed entries of the EFA. In one embodiment, some features correspond to on-chip hardware cryptographic acceleration. By preventing the ability to re-enable these features after shipping, it is possible to send semiconductor chips to foreign countries with only predetermined features enabled and no threat of disabled features being later enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.