High speed programming of programmable logic devices
US7795909B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Sep 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device that receives and stores configuration data in configurable random-access-memory has differential signal input buffer circuitry for receiving the configuration data from a configuration device in differential signal form at high speeds. The programmable logic device may have clock and data recovery circuitry that receives a reference clock and that generates a corresponding internal clock that is used for receiving the configuration data. Error detection circuitry may be used to detect errors occurring during data transmission. The configuration device may have a serializer that serializes parallel configuration data received from memory and differential signal output driver circuitry that provides the configuration data in differential signal form to the programmable logic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.