Charge redistribution successive approximation analog-to-digital converter and related operating method
US7796079B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2009 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Apr 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The analog-to-digital converter provided herein includes a capacitor bank comprising a plurality of binary-weighted capacitors, an operational amplifier having an inverting input node, a noninverting input node coupled to analog ground, and an output node, a reset switch, and an input switch. The reset switch is located between the capacitor bank and the operational amplifier, and it selectively couples the capacitor bank to the inverting input node. The input switch has its common terminal coupled to the capacitor bank, and the input switch selectively couples the capacitor bank to either an analog input voltage, a floating terminal, or analog ground. The capacitor bank includes N binary-weighted capacitors and one balancing capacitor that has a unit capacitance. During operation, the analog-to-digital converter generates an N-bit digital output and one polarity bit from the analog input voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.