Reading method for MLC memory and reading circuit using the same
US7796436B2 · kind B2 · utility
2Cited by
2References
4Claims
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Key dates
| Filing date | Jul 3, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Oct 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.