Semiconductor memory device and write method thereof
US7796439B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | May 10, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.