Self-feedback control pipeline architecture for memory read path applications
US7796463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Sep 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.