Programmable asynchronous first-in-first-out (FIFO) structure with merging capability
US7796652B2 · kind B2 · utility
66Cited by
4References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2007 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Dec 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Where high speed communication between a host and memory devices is carried over serial bit lanes, memory buffers are required for converting buffering the serial bit lanes, and for converting between serial and parallel formats. In addition, jitter, wander, and skew between the bit lanes need to be accommodated. The invention discloses a programmable asynchronous FIFO with the integrated ability to convert blocks of bits from serial to parallel as well as inserting bits from a parallel bus into the serial bit stream. The invention provides very low latency and can be implemented in low power technologies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.