Built-in self-test of 3-dimensional semiconductor memory arrays
US7797594B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2007 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Mar 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for testing a three dimensional (3D) memory including a static array and an active array. The method is performed by a memory built-in self-test (MBIST) controller, and includes writing data to the static array, transferring data from the static array to the active array, and reading data from the active array. The method further includes, in a plurality of subsequent cycles, writing data to the static array; transferring data from static array to the active array, and reading data from the active array, wherein said writing data for each subsequent cycle is performed concurrently with reading data for a previous cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.