Serially decoded digital device testing
US7797595B2 · kind B2 · utility
1Cited by
6References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 18, 2008 |
| Grant date | Sep 14, 2010 |
| Priority date | — |
| Expiry date | Apr 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Testing of memories that decode a serial stream of address data to access the memory may be performed by either successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.