Patent · US Active

Low power decompression of test cubes

US7797603B2 · kind B2 · utility

42Cited by

11References

36Claims

0Family size

Inventors

Janusz Rajski · West Linn, US
Grzegorz Mrugalski · Ostróda, PL
Dariusz Czysz · Poznań, PL
Jerzy Tyszer · Poznań, PL

Key dates

Filing date	Jul 19, 2007
Grant date	Sep 14, 2010
Priority date	—
Expiry date	Nov 8, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318335
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.