Method for manufacturing a CMOS device having dual metal gate
US7799630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2008 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Jun 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
Abstract
A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.