Nonvolatile semiconductor memory device and manufacturing method thereof

US7800091B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Takeshi Kamigaichi · Yokohama, JP
• Hirofumi Inoue · Kamakura, JP

Key dates

• Filing date: Apr 24, 2008
• Grant date: Sep 21, 2010
• Expiry date: Sep 1, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8836

Abstract

A nonvolatile semiconductor memory device includes a first stacked structure in which a plurality of electrode layers are stacked on a substrate via insulating layers, a first resistance changing layer provided on a side surface of the first stacked structure and in contact with the first electrode layers, the first resistance changing layer having a resistance value changing on the basis of an applied voltage, a second electrode layer provided on a side surface of the first resistance changing layer, and a bit line provided on the first stacked structure and electrically connected to the second electrode layer.