Power device package
US7800224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2007 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Feb 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/2076
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power device package according to the one embodiment of the present invention includes an insulating substrate with an interconnection pattern disposed on the insulating substrate. The interconnection pattern comprises a single conductive layer comprising a first metal layer, and a multiple conductive layer comprising another first metal layer and a second metal layer disposed on the another first metal layer. A plurality of wires are attached to an upper surface of the single conductive layer and/or an upper surface of the second metal layer of the multiple conductive layer. Contact pads on a power control semiconductor chip and a low power semiconductor chip driving the power control semiconductor chip are electrically connected to the wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.