Multiple voltage mode pre-charging and selective level shifting
US7800407B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Jun 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To pre-charge a node to one of first and second voltage levels in response to inputs received at the corresponding voltage level, to selectively level shift the node from the first voltage level to the second voltage level when in a first voltage mode, and to maintain the node at the second voltage level when in a second voltage mode. Level shifting from first voltage level may be performed within one gate stage that may be bypassed when in the second voltage mode. The node may be discharged with no delay difference between the first and second voltage modes. Inputs may include a clock signal, which may be received at either of the first and second voltage levels without level shifting the clock signal. A circuit may be implemented with a multi-core processor system to permit selective voltage mode operation of the cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.