Wafer burn-in test circuit
US7800964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2008 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Nov 29, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wafer burn-in test circuit includes an address toggle signal generating unit for generating an address toggle signal in response to address signals having a constant time period, a reset signal generating unit for receiving a wafer burn-in mode activation signal, the address signals, and a reset determination signal among the address signals and then generating a reset signal, a refresh test mode signal generating unit for receiving the address toggle signal and the reset signal and then generating a refresh test mode signal, and a refresh period signal generating unit for receiving the address toggle signal and the refresh test mode signal and then generating a refresh period signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.