Virtually-tagged instruction cache with physically-tagged behavior
US7802055B2 · kind B2 · utility
4Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2006 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Jul 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.