Loading test data into execution units in a graphics card to test execution
US7802146B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2007 |
| Grant date | Sep 21, 2010 |
| Priority date | — |
| Expiry date | Aug 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a method and system for loading test data into execution units in a graphics card to test the execution units. Test instructions are loaded into a cache in a graphics module comprising multiple execution units coupled to the cache on a bus during a design test mode. The cache instructions are concurrently transferred to an instruction queue of each execution unit to concurrently load the cache instructions into the instruction queues of the execution units. The execution units concurrently execute the cache instructions to fetch test instructions from the cache to load into memories of the execution units and execute during the design test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.