Patent · US Active

Memory controller, memory circuit and memory system with a memory controller and a memory circuit

US7802166B2 · kind B2 · utility

10Cited by

3References

17Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Aaron Nygren · Birkenfeld, DE
Thomas Hein · Hersbruck, DE
Martin Maier · Asperg, DE
Otto Schumacher · Dachau, DE

Key dates

Filing date	Sep 27, 2006
Grant date	Sep 21, 2010
Priority date	—
Expiry date	Jul 20, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1004
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Methods and apparatus for adjusting a phase difference between clock signals. A first clock signal at a memory controller is adjusted relative to a clock second signal at a memory device. In one embodiment, data is transferred to the memory device according to the first clock signal, which has a predetermined phase relationship with second clock signal. Data received at the memory device is sampled at the memory device according to the second clock signal. Analysis is done of the data on the memory controller and of the received data on the memory circuit. On the basis of the analysis, an adjustment may be made to the phase relationship.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.