Aaron Nygren
44Patents
7h-index
26Co-inventors
69Inventor score
Filing activity: Dec 14, 2000 → Dec 20, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7836386B2 | Phase shift adjusting method and circuit | Electricity | 28 | Active |
| US6717832B2 | Method for data communication between a plurality of semiconductor modules and a controller module and semiconductor module configured for that purpose | Physics | 15 | Expired |
| US6728144B2 | Method and circuit configuration for generating a data strobe signal for very fast semiconductor memory systems | Physics | 13 | Expired |
| US8730758B2 | Adjustment of write timing in a memory device | Physics | 11 | Active |
| US7802166B2 | Memory controller, memory circuit and memory system with a memory controller and a memory circuit | Physics | 10 | Active |
| US6946848B2 | Calibration configuration | Physics | 10 | Expired |
| US7411862B2 | Control signal training | Physics | 9 | Active |
| US8489912B2 | Command protocol for adjustment of write timing delay | Physics | 7 | Active |
| US8909840B2 | Data bus inversion coding | Emerging Cross-Sectional Technologies | 7 | Active |
| US7844888B2 | Electronic device, method for operating an electronic device, memory circuit and method of operating a memory circuit | Physics | 6 | Active |
| US8726139B2 | Unified data masking, data poisoning, and data bus inversion signaling | Emerging Cross-Sectional Technologies | 6 | Active |
| US7414435B2 | Circuit arrangement and method for converting logic signal levels and use of the circuit arrangement | Electricity | 4 | Active |
| US7024326B2 | Method of optimizing the timing between signals | Electricity | 4 | Expired |
| US8862966B2 | Adjustment of write timing based on error detection techniques | Physics | 4 | Active |
| US6701473B2 | Electrical circuit and method for testing a circuit component of the electrical circuit | Physics | 4 | Expired |
| US7304495B2 | Pseudodynamic off-chip driver calibration | Electricity | 3 | Expired |
| US7391245B2 | Delay locked loop and method for setting a delay chain | Electricity | 3 | Active |
| US10482043B2 | Nondeterministic memory access requests to non-volatile memory | Physics | 2 | Active |
| US8782458B2 | System and method of data communications between electronic devices | Physics | 2 | Active |
| US11854602B2 | Read clock start and stop for synchronous memories | Physics | 2 | Active |
| US8201071B2 | Information transmission and reception | Electricity | 2 | Active |
| US6715012B2 | Bus system | Physics | 1 | Expired |
| US7440349B2 | Integrated semiconductor memory with determination of a chip temperature | Physics | 1 | Active |
| US8161344B2 | Circuits and methods for error coding data blocks | Physics | 1 | Active |
| US12002541B2 | Read clock toggle at configurable PAM levels | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.