Transistor and fabrication process
US7803668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2007 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Nov 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6744
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having an insulating substrate including, for example, based on silicon oxide. Transistor also includes a conducting gate region comprising, for example, TiN or polysilicon, formed on a localized zone of the upper surface of the substrate, and an isolating region, comprising, for example, silicon oxide and surrounding the conducting region. The conducting region is also bounded in the direction normal to the plane of the drawing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.