Method of forming a vertical diode and method of manufacturing a semiconductor device using the same
US7803679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2008 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Apr 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.