Test device for determining charge damage to a transistor
US7804317B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2006 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Jul 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
According to one exemplary embodiment, a test device includes a transistor situated on a substrate. The test device further includes a protection device coupled by a fuse to a gate of the transistor in an interconnect metal layer, where the interconnect metal layer is formed over the substrate. The fuse allows the protection device to be decoupled from the gate of the transistor prior to testing the transistor. The test device further includes first and second contact pads formed over the substrate and coupled to respective terminals of the fuse to provide access to the fuse. A current can be applied between the first and second contacts pads to cause the fuse to open to decouple the protection device from the gate of the transistor. The test device further includes an antenna coupled to the gate of the transistor with interconnect metal segments for accumulating electrical charge during wafer processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.