Overlay key, method of forming the overlay key and method of measuring overlay accuracy using the overlay key
US7804596B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2006 |
| Grant date | Sep 28, 2010 |
| Priority date | — |
| Expiry date | Jun 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an overlay key used for measuring overlay accuracy between first and second layers on a substrate, a first mark may be formed in the first layer, and a second mark may be formed on the second layer. The first mark may include first patterns having a first pitch and extending in a first direction. The second mark may include second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch. First and second images may be acquired from the first and second marks. The overlay accuracy may be produced from position information of first and second interference fringes formed by overlaying a test image having a third pitch onto the first and second images.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.