Method for manufacturing a layer arrangement and layer arrangement

US7807563B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Zvonimir Gabric · Zorneding, DE
• Werner Pamler · Munich, DE
• Guenther Schindler · Hersbruck, DE
• Gernot Steinlesberger · Munich, DE
• Andreas Stich · Kleinmachnow, DE
• Martin Traving · Unterhaching, DE
• Eugen Unger · Augsburg, DE

Key dates

• Filing date: Apr 12, 2007
• Grant date: Oct 5, 2010
• Expiry date: Apr 12, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.