Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices
US7807576B2 · kind B2 · utility
13Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Jun 20, 2008 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Sep 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.