Fabrication of integrated circuits with isolation trenches
US7807577B2 · kind B2 · utility
0Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2008 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Jan 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.