Processed wafer via
US7808111B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Nov 6, 2006 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Jan 3, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24174
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.