Monolithically integrated multiplexer-translator-demultiplexer circuit and method
US7808274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2007 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Feb 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A monolithically integrated multiplexer-translator-demultiplexer and a method for multiplexing and translating an electrical signal or demultiplexing and translating an electrical signal. A multiplexer and a demultiplexer are monolithically integrated with a translator. Circuits that operate at different voltage supply levels from each other may be coupled to the multiplexer and a circuit that operates at a different voltage supply level from the circuits coupled to the multiplexer or that operates at the same voltage supply level as at least one of the circuits coupled to the multiplexer is coupled to the demultiplexer. The monolithically integrated multiplexer-translator-demultiplexer selects a signal from one of the circuits coupled to the multiplexer, translates its voltage level and provides the translated signal level as an output signal. Alternatively, the monolithically integrated multiplexer-translator-demultiplexer creates demultiplexed signals from an electrical signal and translates the voltage levels of the demultiplexed signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.