Robust 8T SRAM cell
US7808812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2008 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Dec 21, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.