Computation parallelization in software reconfigurable all digital phase lock loop
US7809927B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2007 |
| Grant date | Oct 5, 2010 |
| Priority date | — |
| Expiry date | Aug 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.