Method for fabricating MOS-FET
US7811873B2 · kind B2 · utility
98Cited by
2References
8Claims
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Key dates
| Filing date | Sep 11, 2007 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Oct 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6706
Abstract
A method for fabricating MOS-FET using a SOI substrate includes a process of ion implantation of an impurity into a channel region in a SOI layer; and a process of channel-annealing in a non-oxidized atmosphere. In the ion implantation process, a concentration peak of the impurity is made to exist in the SOI layer. Moreover in the channel-annealing process, the impurity is distributed with a high concentration in the vicinity of the surface of the SOI layer under the following condition with the anneal temperature as T (K) and annealing time as t (minutes):506×1000/T−490<t<400×1000/T−386.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.