Shallow trench isolation stress adjuster for MOS transistor
US7811893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2009 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Jun 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an active area (105) in a substrate (115), wherein the active area (105) is bounded by an isolation structure (120). The method further includes placing at least one stress adjuster (130) adjacent the active area (105), wherein the stress adjuster (130) is positioned to modify a mobility of a majority carrier within a channel region (155) of the MOS transistor (100). Other embodiments of the present invention include a MOS transistor device (200) and a process (300) for constructing an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.